Electronic equipment such as a cellular phone and a digital camera has been requested to be reduced in size with higher functionality. Accordingly, semiconductor modules in which semiconductor devices and chips are stacked and combined (Package on Package (PoP)) have been particularly developed for electronic components. In PoP mounting, it has been necessary to improve the connection yields of upper and lower packages in response to higher density and improve the sensitivity of inspection in response to higher functionality. Accordingly, it has been requested to enhance inspection yields by improved quality.
Patent document 1 (Japanese Patent Laid-Open No. 2004-363126) describes a laminated structure as a known semiconductor module of the related art.
FIGS. 17A and 17B show patent document 1 (Japanese Patent Laid-Open No. 2004-363126).
A semiconductor package 200 is stacked and mounted on a semiconductor package 100. On the underside of the semiconductor package 100, connection terminals 2 are disposed. On the top surface of the semiconductor package 100, connection terminals 1 are disposed. In a non-defective product, the connection terminals 1 are joined onto connection pads 3 formed on the top surface of the semiconductor package 100. The connected surfaces of the connection terminals 1 and 2 are similarly shaped like circles and the connection pads 3 are also circular in shape. In this configuration, the layouts of the semiconductor packages 100 and 200 are optimized regardless of the layouts of the connection terminals 1 and 2. In a transparent image of the semiconductor module observed from above, the connection terminals 1 and 2 mostly overlap each other.
Patent document 2 (Japanese Patent Laid-Open No. 2008-294014) describes a known example of stacked printed circuit boards, each having a semiconductor package mounted thereon. FIGS. 18A, 18B, and 18C show patent document 2 (Japanese Patent Laid-Open No. 2008-294014).
In the example of FIG. 18A, printed circuit boards 100a and 100b are stacked. On electrode pads 30b of the upper printed circuit board 100b, a semiconductor package 1b is mounted via melted and solidified ball electrodes 10b. On electrode pads 30a of the lower printed circuit board 100a, a semiconductor package 1a is mounted via melted and solidified ball electrodes 10a. 
FIG. 18B is a plan view showing the electrode pads 30b and FIG. 18C is a plan view showing the electrode pads 30a. In a transparent image of the stacked printed circuit boards 100a and 100b that are observed from above, the electrode pads 30a and 30b have projecting portions in the planar direction and are oriented in opposite directions such that the electrode pads do not overlap each other.